Although semiconductor apparatuses integrating power MOS devices for the switching devices thereof are used for switching power supply ICs and driver ICs mounted on hand held electronic equipment and data communication equipment, on-resistance reduction and switching characteristics improvement for the power MOS devices pose problems which should be obviated. First, a trench lateral power MOS device (a trench lateral power MOSFET: hereinafter referred to simply as a “TLPM”), which integrates switching devices including trenches therein with high integration density and exhibits low on-resistance, will be described below.
The TLPM has been attracting much attention, since the TLPM has achieved low on-resistance (60% as high as the on-resistance of the conventional lateral planar power MOS device) by shortening the device pitch and increasing the channel width density, and since the TLPM has realized excellent switching characteristics by reducing the feedback capacitance and the channel capacitance thereof.
FIG. 9 is a cross-sectional view of a TLPM employing a conventional technique.
Referring to FIG. 9, the conventional TLPM 1 includes a p−-type semiconductor substrate 1, a trench 11 formed from the surface of semiconductor substrate 1, an n-type drain region 12 surrounding the sidewall and the bottom of trench 11, and an n-type plug region 13 formed in the bottom of trench 11. TLPM 1 further includes an n+-type source region 14 formed in a p-type offset region 15 around the upper portion of trench 11.
Source electrodes 16 are formed around the aperture of trench 1. A drain electrode 17 is formed on the surface of semiconductor substrate 1 between source electrodes 16. A polysilicon gate electrode 19 is formed in trench 11 such that gate electrode 19 is facing toward p-type offset region 15 across a gate oxide film 18. A polysilicon drain connection conductor 20 connects n-type drain region 12 and drain electrode 17 to each other. Gate electrode 19, drain connection conductor 20 and a source connection conductor 21 are insulated from each other by an insulator film 22 formed into a unit with gate oxide film 18.
It is important for the process of manufacturing TLPM 10 to form a silicon oxide (SiO2) film selectively in the bottom of trench 11 or to form the oxide film to be thicker on the bottom of trench 11 than on the sidewall of trench 11. In these days, techniques for manufacturing a trench MOS device are known. The techniques facilitate reducing the capacitance between the gate and drain (Cgd) by the discriminative oxidation using the shadowing effects obtained by oblique ion implantation and providing the trench MOS device with high mutual inductance (gm, max.) and low on-resistance important for optimal amplification and switching of linear signals (cf. U.S. Patent Specification 2003/0235959 A).
FIGS. 10A through 10C are cross-sectional views illustrating the steps for selectively forming an oxide film in a trench. N+ ions (nitrogen ions) are implanted obliquely only into silicon in the sidewall of a trench 100 so that ion implantation into the bottom of trench 100 may be avoided (cf. the oblique nitrogen ion implantation shown in FIG. 10A). By the oblique nitrogen ion implantation, an oxidation-resistive mask region 101 of nitrogen-doped silicon or a silicon nitride film is formed in the sidewall of trench 100. As a result, oxidation-resistive mask region 101 distributes as shown in FIG. 10B. In the subsequent thermal oxidation, an insulator layer grows slowly in oxidation-resistive mask region 101, in which N+ ions have been implanted. By using this, an oxide film 102 in the trench bottom may be made to be thicker than the not shown oxide film formed in the sidewall of trench 100 (cf. FIG. 10C).
The method for forming an oxide film as described above is different from the usual method, which forms various oxide films over the entire surface and, then, removes the unnecessary oxide films by etching. The above-described method for oxide film formation is the so-called local oxidation of silicon (hereinafter, referred to simply as the “LOCOS”) that grows an oxide film locally (selectively) on a silicon wafer. The LOCOS is used to form a field oxide film for device separation. Growth of a LOCOS oxide film adjacent to a nitride film sometimes exhibits the effects called “encroachment”.
FIGS. 11A and 11B are cross-sectional views illustrating the steps of selective oxidation using a nitrogen-doped silicon film or a nitride film for an oxidation-resistive mask. In the planar process, a nitrogen-doped silicon film or a silicon nitride (Si3N4) film is arranged locally on a silicon wafer 110 for an oxidation-resistive mask 111. A thin silicon oxide film 112 is disposed below oxidation-resistive mask 111. Then, silicon oxide film 112 is oxidized selectively as shown in FIG. 11B. Since silicon wafer 110 is oxidized simultaneously with the selective oxidation of silicon oxide film 112, a LOCOS oxide film 113 is formed as shown in FIG. 11B. As LOCOS oxide film 113 is formed, silicon oxide film 112 is grown and expanded on the major surface of silicon wafer 110 and oxidation-resistive mask 111 is lifted somewhat from silicon wafer 110. Due to the lifting of oxidation-resistive mask 111, LOCOS oxide film 113 is shaped with the so-called “bird's beak” below the edge portion of oxidation-resistive mask 111.
The trouble due to the bird's beak shape is caused also in oxide film 102 in the trench bottom shown in FIG. 10C. Oxide film 112 sinking below oxidation-resistive mask 111 exerts stress to the inside of silicon wafer 110, causing crystal defects therein.
Published U.S. Patent Specification 2003/0235959A describes the method for implanting Ar ions at a high dose amount vertically into a silicon wafer including trenches formed therein so that the Ar ions may be implanted only into the trench bottom and so that the implantation thereof into the trench sidewall may be avoided. Since the oxidation rate of silicon in the trench bottom is increased by the Ar ion implantation thereto, a thick oxide film may be formed in the trench bottom by the subsequent thermal oxidation process.    [Non-Patent Document 1] C. Dominguez, B. Garrido, J. Montserrat, J. R. Morante and J. Samitier, “Etching rate modification in SiO2 by ion implantation and thermal annealing.” Nuclear Instruments and Methods in Physics Research, B80/81 (1993) p.p. 1367-1370
Since the discriminative oxidation described in Published U.S. Patent Specification 2003/0235959A dopes the silicon layer around trench 100 directly with nitrogen by ion implantation, the nitrogen in oxidation-resistive mask region 101 of nitrogen-doped silicon, or of a nitride film, is sometimes not completely consumed by thermal oxidation. If the nitrogen-doped silicon remains in the trench sidewall, nitrogen will be left in the silicon layer without being expelled to the outside even by a heat treatment performed for a long time at a high temperature, since the bonding force between silicon and nitrogen is very strong. It has been known that the diffusion coefficient of boron (B), phosphorus (P) and such a dopant is reduced greatly in nitrogen-doped silicon. If nitrogen is doped locally in the trench sidewall, the device characteristics will be impaired due to a reduction of carrier mobility, stress generation and other such causes.
As shown in FIG. 11B, LOCOS oxide film 113 is shaped with a bird's beak below the edge portion of oxidation-resistive mask 111 by oxidant encroachment. If similar oxidant encroachment occurs in both edge portions of oxidation-resistive mask region 101 formed on the trench sidewall shown in FIGS. 10B and 10C, the resulting stress in the edge portions of oxidation-resistive mask region 101 will further cause crystal defects to occur or the flatness of the trench sidewall will be impaired.
A thick oxide film may be formed selectively in the lower portion of the trench sidewall or in the bottom of trench by thermal oxidation in a process for manufacturing a trench-type semiconductor device in which a nitrogen-doped silicon layer or a nitride film is formed for an oxidation-resistive mask by selectively implanting N+ ions obliquely into the silicon layer around the trench sidewall. However, several adverse effects will occur, including for example, (1) the characteristics and reliability of the device will be impaired by the residual nitrogen, (2) crystal defects and stress will be caused by the oxidation, (3) the characteristics and the reliability of the device will be impaired also by stress resulting from formation of a bird's beak.
Since argon gas is inert and argon is electrically inactive in silicon, argon atoms may be expelled outside a silicon wafer by a high-temperature thermal treatment (out-diffusion). Therefore, argon ion implantation into the trench bottom is advantageous for reducing the concentrations of argon and such impurities.
When a silicon wafer, into which argon ions are implanted, is treated thermally, the argon gas condenses in the silicon wafer during the heat treatment, causing vacancy-type defects called “micro bubbles.” The micro bubbles are liable to adsorb heavy metals, impairing the device characteristics. Thus, the micro bubbles also cause a troublesome reduction in carrier mobility.
In view of the foregoing, it would be desirable to provide a method for manufacturing a semiconductor device that facilitates forming a thick oxide film selectively and easily on the bottom of a trench and on the sidewall near the bottom of the trench.